1433215829
发表于 2015-11-4 09:52:50
啊啊啊
vvvvvvvvvvvvvvv
发表于 2015-11-4 16:39:18
666666666666666
杉杉*
发表于 2015-11-5 13:51:41
告诉吗我怎么弄
hjy1234*
发表于 2015-11-5 22:46:06
我想看看是什么问题
ytc*
发表于 2015-11-7 17:04:14
看看,不错。很好。
喜剧之王*
发表于 2015-11-7 17:53:07
安装程序UI模式出错的解决方法
qewtqwqqq
发表于 2015-11-8 21:22:36
Institute of Microelectronics of Chinese Academy of Sciences. Working with senior colleagues, I was mainly responsible building the frequency input control part of the whole scanner using zc702 demoboard In the process of development, I firstly programmed VerilogHDL sequential logic in ISE according to the corresponding input of different frequencies. After simulating with testbench, and the synthesis result identified with ideal waveform, I generate user files and UCF file to allocate FPGA pins, and laid out the design into FPGA board. Lastly, I connected the board to the test module, changed input and measured output frequency, thus modified program according to the differences between results and ideal to finally obtain the FPGA board with correct user files. During the two-month internship, I applied the knowledge of embedding and Verilog Language into experiment, and with the whole procedure being conducted independently numbers of times, I was gradually equipped with knowledge and experience which could be of use in more complex designing in the future.
Furthermore, I gained much experience in Verilog programming and debugging, which is totally different with that of C. C allows people to program through different angles, conducting different programs to acheive the same function, while in Verilog there always exist a single access, which required people a more rigorous programming mind.
盐粥还是热的
发表于 2015-11-10 00:09:38
求大神解决问题,谢谢了,谢谢了
杨子@
发表于 2015-11-10 12:28:09
学习学习学习
1234141
发表于 2015-11-10 20:59:02
{:smile:}